1. Field of the Invention
This invention relates to a system for producing semiconductor devices and, more particularly, to a system for successively and continuously processing semiconductor substrates (wafers).
Usually, semiconductor devices are produced continuously and consistently by coupling individual process stations or units, which perform respective predetermined processes on semiconductor wafers, to one another by a conveying mechanism for conveying the semiconductor wafers.
In the prior art system, however, the entire processing system for producing semiconductor devices must be stopped when a fault occurs in any of the process stations or units or a part of the conveying mechanism, and if the recovery of the system requires a long time, a great reduction of the productivity and disarrangement of the production schedule occurs.
Therefore, the processing system should be capable of operating even when a part thereof is under maintenance due to a fault occurrence.
2. Description of the Related Art
(1) Processing for Producing Semiconductor Devices
In the production of a large quantity of a few kinds of products such as DRAM's (dynamic random access memories), a plurality of production process steps can not be carried out at one time in the same semiconductor wafer processing system, and therefore, semiconductor devices can be produced only by processing semiconductor wafers in a proper order and by a fixed procedure.
On the other hand, in the production of a small quantity of many kinds of products such as ASIC (application specific integrated circuits), a plurality of process steps must be carried out simultaneously in a semiconductor wafer processing system to meet a given term.
Currently, a continuous semiconductor wafer processing system having a wide freedom of choice of many different process steps is required, to meet the demand for a small quantity of many different kinds of semiconductor device products, including ASIC.
(2) Example of Prior Art Continuous Processing System
A prior art continuous processing system is disclosed in Japanese Patent Publication 59-31211, corresponding to USP 3946484, and FIG. 1 is a schematic plan view of this disclosed system.
The system comprises independent wafer-processing stations or units 1A to 1F and a central conveying unit 2 for transferring wafers to and from the individual stations or units by a reciprocal operation. A continuous processing of wafers is made possible by coupling the individual process stations or units with the central conveying unit 2.
As an example, a processing procedure for manufacturing FET (field effect transistor) will now be described.
(1) Wafers are supplied from a Loader 3 to an initial oxidization station 1A.
(2) Cleaning of the wafer surface, formation of an initial oxide film, and coating of a photoresist are carried out in the initial oxidization station 1A.
(3) The central conveying unit 2 picks up wafers after the process step (2) and conveys them to a photoresist exposure station 1D.
(4) Exposure by a predetermined pattern is made in the photoresist exposure station 1D.
(5) The central conveying unit 2 picks up wafers after the process step (4) and conveys them to a drain station 1B.
(6) Development of the photoresist, etching of the oxide film, and formation of a drain region by diffusion are carried out in the drain station 1B.
The photoresist is then coated.
(7) The central conveying station 2 picks up wafers after the process step (6) and conveys them again to the photoresist exposure station 1D.
(8) A gate region pattern exposure is carried out in the photoresist exposure station 1D.
(9) The central conveying unit 2 picks up wafers after the process step (8) and conveys them to a gate station 1C.
(10) Development of the photoresist, etching and the formation of an oxide film are carried out in the gate oxidation station 1C.
The photoresist is again coated.
(11) The central conveying unit 2 picks up wafers after the process (10) and conveys them to the photoresist exposure station 1D again.
(12) Exposure to a predetermined pattern is carried out in the photoresist exposure station 1D.
(13) The central conveying unit 2 picks up wafers after process (12) and conveys them to a metallization station 1E.
(14) Development of the photoresist, etching, and a metallization of the wafer surface are carried out in the metallization station 1E.
The photoresist is again coated.
(15) The central conveying unit 2 picks up wafers after the process (14) and conveys them to the photoresist exposure station 1D again.
(16) Exposure by a predetermined pattern is made in the photoresist exposure station 1D.
(17) The central conveying unit 2 picks up wafers after the process step (16) and conveys them to a sintering station 1F.
Development of the photoresist, etching of the metallic film, and sintering of the wafer are carried out in the sintering station 1F.
Thereafter, the wafers are collected in an unloader 104, thus ending the processing of the wafers.
As shown above, a series of processes on the wafers is completed by conveying wafers to individual process stations for processing wafers in a predetermined sequence.
In the above processing system, however, once a fault occurs in any of the process stations IA to 1F or in a part of the central conveying unit 2, the series of wafer processing steps can no longer be continued, that is, the entire processing system must be stopped, thus leading to an extreme reduction of the productivity and a disturbance of the production schedule.
In addition, the processing in this case gives priority to the processing of preceding wafers. This means that the speed of processing (or processing time of) a succeeding wafer is prescribed by the speed of processing a preceding wafer. In other words, the processing efficiency is determined by the processing time of the slowest process station, i.e., the station operating at the lowest processing speed of all the process stations.
Therefore, where a plurality of different kinds of products are produced, the throughput of the processing system is greatly reduced due to the differences in the processing times of the various process steps at the corresponding stations.